Espressif Systems /ESP32-C2 /EXTMEM /CORE0_ACS_CACHE_INT_CLR

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Interpret as CORE0_ACS_CACHE_INT_CLR

Description

This description will be updated in the near future.

Fields

CORE0_IBUS_ACS_MSK_IC_INT_CLR	The bit is used to clear interrupt by cpu access icache while the corresponding ibus is disabled or icache is disabled which include speculative access.
CORE0_IBUS_WR_IC_INT_CLR	The bit is used to clear interrupt by ibus trying to write icache
CORE0_IBUS_REJECT_INT_CLR	The bit is used to clear interrupt by authentication fail.
CORE0_DBUS_ACS_MSK_IC_INT_CLR	The bit is used to clear interrupt by cpu access icache while the corresponding dbus is disabled or icache is disabled which include speculative access.
CORE0_DBUS_REJECT_INT_CLR	The bit is used to clear interrupt by authentication fail.
CORE0_DBUS_WR_IC_INT_CLR	The bit is used to clear interrupt by dbus trying to write icache

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